RezwanAhmed & His Team || Software Engineer

CISC :: RISC | Processor

Processor | CISC & RISC

CISC Processor | 

—CISC stands for Complex Instruction Set Computer. —CISC are chips that are easy to program and which make efficient use of memory. Examples of CISC processors are: —PDP-11, —Motorola 68000 family, Intel x86/Pentium CPU’s.

—CISC History |
The first PC microprocessors developed were CISC chips, because all the instructions the processor could execute were built into the chip. —Memory was expensive in the early days of PCs, and CISC chips saved memory because their programming could be fed directly into the processor. CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor.

For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this.

Characteristic Of CISC Design |

—CISC instruction sets have some common characteristics:

  • —A 2-operand format, where instructions have a source and a destination.
  • Register to register, register to memory, and memory to register commands.
  • Multiple addressing modes for memory, including specialized modes for indexing through arrays
  • —Variable length instructions where the length often varies according to the addressing mode
  • Instructions which require multiple clock cycles to execute.

—Hardware architectures : CISC hardware architectures have several characteristics in common:

  • —Complex instruction-decoding logic, driven by the need for a single instruction to support multiple addressing modes.
  • —A small number of general purpose registers. This is the direct result of having instructions which can operate directly on memory and the limited amount of chip space not dedicated to instruction decoding, execution, and microcode storage.
  • —Several special purpose registers. Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design.
  • —A “Condition code” register which is set as a side-effect of most instructions.

CISC and the Classic Performance Equation

  • The equation for determining performance is the sum for all instructions of (the number of cycles per instruction * instruction cycle time) = execution time. 
  • This allows you to speed up a processor in 3 different ways : use fewer instructions for a given task, reduce the number of cycles for some instructions, or speed up the clock (decrease the cycle time.)
  • —CISC tries to reduce the number of instructions for a program

RISC Processor |


The circuitry that performs the actions defined by the microcode in many (but not all) CISC processors is, in itself, a processor which in many ways is reminiscent in structure to very early CPU designs.

In the early 1970s, this gave rise to ideas to return to simpler processor designs in order to make it more feasible to cope without (then relatively large and expensive) ROM tables and/or PLA structures for sequencing and/or decoding. The first (retroactively) RISC-labeled Processor (IBM 801IBMs Watson Research Center, mid-1970s) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or an engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger public. Simplicity and regularity also in the visible instruction set would make it easier to implement overlapping processor stages (pipelining) at the machine code level (i.e. the level seen by compilers.) However, pipelining at that level was already used in some high performance CISC “supercomputers” in order to reduce the instruction cycle time (despite the complications of implementing within the limited component count and wiring complexity feasible at the time). Internal microcode execution on CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.