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Fast Graphene CPUs : Out How To Make Lightning


Fast Graphene CPUs – Scientists Just Figured Out How To Make Lightning

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Graphene has the power to change computing forever by making the fastest transistors ever. Fortunately, scientists have just taken a big step closer to making Graphene transistors work for real.

Graphene transistors aren’t just fast; they’re lightning fast. The speediest one to date clocked in at some 427GHz. That’s orders of magnitude more than what you can tease out of today’s processors. The problem with Graphene transistors though is that they aren’t particularly good at turning off. They don’t turn off at all actually, which makes it hard to use them as switches.

Now, Guanxiong Liu and a team of researchers at the University of California, Riverside have come up with a practical, highly technical solution. It boils down to “don’t treat Graphene like it’s silicon”.

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MIT’s Technology Review explains:

[Liu and the team] rely on a different phenomenon called negative resistance to create transistor-like behavior.

Negative resistance is the counterintuitive phenomenon in which a current entering a material causes the voltage across it to drop. Various groups, including this one at Riverside, have shown that Graphene demonstrates negative resistance in certain circumstances.

Their idea is to take a standard graphene field-effect transistor and find the circumstances in which it demonstrates negative resistance (or negative differential resistance, as they call it). They then use the dip in voltage, like a kind of switch, to perform logic.

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This strategy allows for functional Graphene circuits that kick silicon’s arse. The only catch is that you have to design them very differently.

Real applications of this tech, as always, are a still way off in the future, and there’s a lot of testing to be done between now and then. But, hey, we’re making progress. One day, we’re going to see this graphene magic actually take off. Let’s just hope it’s at least kind of soon-ish.

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Interested person can detail more from this file :: High Performance Computing 4th Gen Core  vpro-overview-paper


Processor | CISC & RISC


CISC Processor | 

—CISC stands for Complex Instruction Set Computer. —CISC are chips that are easy to program and which make efficient use of memory. Examples of CISC processors are: —PDP-11, —Motorola 68000 family, Intel x86/Pentium CPU’s.

—CISC History |
The first PC microprocessors developed were CISC chips, because all the instructions the processor could execute were built into the chip. —Memory was expensive in the early days of PCs, and CISC chips saved memory because their programming could be fed directly into the processor. CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor.

For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this.

Characteristic Of CISC Design |

—CISC instruction sets have some common characteristics:

  • —A 2-operand format, where instructions have a source and a destination.
  • Register to register, register to memory, and memory to register commands.
  • Multiple addressing modes for memory, including specialized modes for indexing through arrays
  • —Variable length instructions where the length often varies according to the addressing mode
  • Instructions which require multiple clock cycles to execute.

—Hardware architectures : CISC hardware architectures have several characteristics in common:

  • —Complex instruction-decoding logic, driven by the need for a single instruction to support multiple addressing modes.
  • —A small number of general purpose registers. This is the direct result of having instructions which can operate directly on memory and the limited amount of chip space not dedicated to instruction decoding, execution, and microcode storage.
  • —Several special purpose registers. Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design.
  • —A “Condition code” register which is set as a side-effect of most instructions.

CISC and the Classic Performance Equation

  • The equation for determining performance is the sum for all instructions of (the number of cycles per instruction * instruction cycle time) = execution time. 
  • This allows you to speed up a processor in 3 different ways : use fewer instructions for a given task, reduce the number of cycles for some instructions, or speed up the clock (decrease the cycle time.)
  • —CISC tries to reduce the number of instructions for a program

RISC Processor |

RISC Idea

The circuitry that performs the actions defined by the microcode in many (but not all) CISC processors is, in itself, a processor which in many ways is reminiscent in structure to very early CPU designs.

In the early 1970s, this gave rise to ideas to return to simpler processor designs in order to make it more feasible to cope without (then relatively large and expensive) ROM tables and/or PLA structures for sequencing and/or decoding. The first (retroactively) RISC-labeled Processor (IBM 801IBMs Watson Research Center, mid-1970s) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or an engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger public. Simplicity and regularity also in the visible instruction set would make it easier to implement overlapping processor stages (pipelining) at the machine code level (i.e. the level seen by compilers.) However, pipelining at that level was already used in some high performance CISC “supercomputers” in order to reduce the instruction cycle time (despite the complications of implementing within the limited component count and wiring complexity feasible at the time). Internal microcode execution on CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.


Zero Instruction Set Computer | ZISC Processor


In computer science, Zero Instruction Set Computer (ZISC) indicates to a computer architecture based on pure pattern matching and absence of (micro-) instructions in the classical sense. The ZISC acronym alludes to the previously developed RISC (Reduced Instruction Set Computer) technology.
                                                                                                                                                                                    English: IBM's Watson computer, Yorktown Heigh... 
ZISC is a technology based on ideas from artificial neural networks and massively hardwired parallel processing. This concept was invented by Guy Paillet.
The ZISC architecture alleviates the memory bottleneck by blending the pattern memory with the pattern learning and recognition logic. The main innovation was finding a way to solve the “winner takes all problem” and allows a constant learning/recognition time, regardless of the number of processing elements (e.g. neurons) connected in parallel.

The first  ZISC35 with 36 neurons was released in 1993 and the ZISC78 in 2000 both by IBM which discontinued the manufacturing in 2001.

In August 2007, the CM1K (CogniMem 1,024 neurons) was introduced by CogniMem Ltd. CM1K was designed by Anne Menendez and Guy Paillet.

Practical uses of ZISC / CogniMem technology focus on pattern recognition, information retrieval (data mining), security and similar tasks.

Abstract |

Implementation of the new IBM Zero Instruction Set Computer (ZISC036) on a PC/ISA-bus card as well as on a VME-card is reported. The ZISC circuit has 36 processing elements of a type similar to that of Radial Basis Function (RBF) neurons. It is a highly parallel and cascadable building block with on-chip  learning capability, and is well suited for pattern recognition,  signal processing, etc.

Introduction |
Figure 1. Figure 1. ZiSC036 block diagram The top  part shows the address (6-bit), control (9-bit) and l/O data (16-bit) buses; the lower part includes the decision output (16-bit) bus. AD buses are directly connected when chlps are cascaded. The 4-bit decision bus (far right) allows the use of the ZISC036 in stand alone mode.

Last summer, IBM presented the first Zero Instruction Set Computer or ZISC036 and recently we presented the first  implementation of this building block on a PC-486 ISA-bus card.

The RCE [5] learning algorithm embedded on-chip. Although this learning concept involves simple commitment of prototype vectors to memory and adjustment of scalar weighting factors, such networks have been shown to define classification boundaries of complicated clustering in multidimensional space. The ZISC036 has a built-in-self-learning mechanism and can handle up to 16382 output categories. These are features that make it well suited for several types of applications.
 
Architecture |

The ZISC036 (figs 1 and 2) is conveniently regarded as a coprocessor device. As such a device, it must be controlled by a micro-controller or a state machine (accessing its registers). In many RBF applications a large number (>100) of neurons is required, which is easily arranged due to the cascadable structure of the ZISC. Indeed, most of its 144 pins can be directly interconnected which simplify the design and allow for “ZISC-towers”. Multi-layer configurations can be accomplished by either connecting several chips or sub setting the network and time-multiplexing the inputs.

Figure 2. Figure 2. Schematic drawing of a single ZISC036  processing element or neuron

The ZISC036 chip supports asynchronous as well as synchronous protocols, the latter when a common clock can be shared with the controller. Examples, of these modes are given in the user’s manual and includes the use of separate address and data buses as well as PCI-like multiplexing, single, multiple and burst transfer.

The calculation of distances between input vectors and prototype uses 14bit precision. The components of the vectors are fed in sequence and processed in parallel by each neuron. This means that for a 20MHz ZISC036, 64 8-bit components can be fed and processed in 3.211µs. The evaluation is obtained in one clock cycle (i.e. 0.511µs) after the feeding of the last component. This corresponds to 250,000 evaluations per second on a 2000 MIPS von Neuman processor. The ZISC036 is fabricated using IBM standard cell CMOS technology and has about 400000 transistors.


Implementations 
Figure 3.  Figure 3. Schematic layout of the VME/ZISC036 board. The lower part shows the piggy-oack area which can hold 4 – 40 ZISC chips.

Although the number of cascaded chips may be application or bus dependent, there should be no problem using up to ten chips. Building larger networks is a matter of grouping small networks together by placing re-powering devices where needed. Bus and CPU interface examples are found in the ZISC036 Data Book.

The present VMEbus card (the reader is referred to ref [2] for details on a IBM/ISA implementation) holds 4 piggy-back PCBs with one chip each. The PCBs are made to carry another card on top and hence up to 40 ZlSCs could in principle be mounted in four “ZISC-towers” on the VME-card.

For the PC/ISA-board, computer codes were written in Borland C++ under DOS and Windows using the ZINC GUI library.

The VME-implementation relies on a VME to SBus hardware interface and pertinent software. This software is written using the GNU C++ and the VMIC SBus interface library.



Results and Summary |

A neural network of the RBF-type [5- 7] is in somewhat different from more conventional architectures. In very general terms the approach is to map an N-dimensional space by prototypes. Each of these prototypes is associated with a category and an influence field representing a part of the N-dimensional space around the prototype. Input vectors within that field are assigned the category of that prototype. (In the ZISC implementation the influence fields are represented by hyper-polygons rather than hyper-spheres as in a more theoretical model. Two user selectable distance norms are supported by the chip. Several prototypes can be associated with one category and influence fields may overlap.

Figure 4.  Flgure 4. Examples of inputs. The input neurons 1 and 2 get their values from either of the two histograms shown here (there are three additional histograms for inputs 3 – 8).

There are several learning algorithms associated with the RBF-architecture, but the most common one are the RCE [5] and RCE-like ones. The one used by the ZISC chip is “RCE-Iike”. A nearest neighbour evaluation is also available.

We have added the Intel ETANN and the Bellcore CLNN32/64 neural nets to the ZISC036 with a LHC physics “benchmark test”. The inputs in this test are the moments and transverse moments of the four leading particles, obtained in a simulation of a LHC search for a heavy Higgs. Two-dimensional plots of these moments (p versus pt), for the leading particle, are shown in fig. 4.

Although only some preliminary results have been obtained, it is fair to say that a system with eight inputs and just 72 RBF-neurons could recognise the Higgs to a level of just above 70% and the background to about 85%. This is almost as good as the CLNN32/64 chips. Further details and results will be presented at the AIHENP-95 conference in Pisa, Italy.

It is mentioned that ZISC036 is the first is a series, which possibly implies more, faster and  ~knowledgeable” neurons in subsequent chips.


Acknowledgements |
The present work is carried out under contract with the Swedish Engineering Research Council, which is gratefully acknowledged. Special thanks are due to M. Jean-Pierre LeBouquin and his co-workers at IBM, Essonnes.
 
The article collect from internet and Zero Instruction Set Computer Research Centre; IBM Essonnes Components Development Laboratory, IBM Microelectronics, ZISC036 Data Book.
 
Rezwan Ahmed | Software Engineer
B.Sc.(Hon's) of Computer Science and Software Engineering| 
Stamford University, Bangladesh.
Masters of International Business and Information System Management | 
Swinburne University of Technology.